The present invention relates to analog-to-digital signal converters, and more particularly, to converters which use a "dual slope" conversion process.
In recent times there has been a great increase in the use of digital methods to provide various manipulations of information signals. A large body of theory has been developed for digital signal processing, and many digital signal processing systems have been put in place by software programs developed for general purpose and special purpose digital computers. More recently, advances in monolithic integrated circuit design and fabrication have lead to monolithic integrated circuit chip microprocessors and dedicated digital signal processors which have greatly increased the use of digital signal processing techniques because such chips can lead to drastic reductions in cost.
Nevertheless, the origin of many of the signals to be processed are of such a nature as to provide the information obtained therefrom in analog signal form. This leads to the requirement for a system which can receive analog input signals and provide a sequence of digitized samples suitable for use in a subsequent digital processing system. A large number of such systems, usually termed analog-to-digital converters or ADCs, are known. Some are specially suited to providing high sampling rates but usually at the cost of accuracy, while others provide highly accurate samples but often at the cost of a slower sampling rate. Various converters representing compromises between sampling rates and accuracy exist.
One well known method for obtaining accurate digital conversion values of samples from analog signals but at a relatively slow sampling rate is the "dual slope" method. In this method, an input analog signal having relatively slow value changes is provided, usually through some sort of a buffer such as an operational amplifier based voltage follower, to an operational amplifier integrator. Each sample of this signal is time integrated for a fixed time duration and stored on the integration capacitor. Thereafter, a negative reference voltage is applied to the integrator until the voltage across the integration capacitor in the operational amplifier integrator substantially returns to zero for that sample. The time taken to discharge this integrator capacitor, kept by a counter driven by a clock, gives a digital representation of the value of the input signal at the time of each sample.
This representation can be shown to depend, in the absence of circuit error sources, on just the value of the reference voltage, the fixed time duration of charging the integrator capacitor and the time of discharge. Thus, at least to first order, the digital representation does not depend on any component values in the system which means a high accuracy can be achieved.
This arrangement, however, cannot provide sampling of negative input analog signals without the addition of at least a further reference voltage of an opposite polarity. Also, this arrangement does not permit sampling differential voltages as a difference between two substantial input analog voltages which is often where information is carried from an analog source or sources.
However, such a conversion scheme can be converted to a differential arrangement using standard operational amplifiers by the use of a so called "instrumentation amplifier" which uses two input operational amplifiers to drive a third operational amplifier. A suitable resistor based feedback loop is provided around each amplifier.
While such an arrangement would provide a differential signal sampling capability, there are also a number of drawbacks. Because the differential voltages in the analog input signals may be small differences between either quite large or quite small pairs of input analog signals, the common mode rejection ratio and the power supply rejection ratio must be very large if unacceptable errors are not to be introduced into the system. This can only be achieved in such an arrangement by use of extremely well matched resistors, so matched over the entire range of operating conditions. In addition, the use of standard operational amplifiers in resistor feedback loops would lead to large ground current voltage drop problems, substantial power consumption, and a large physical size when implemented in monolithic integrated circuit form because of the need to supply substantial currents through the resistors.
Thus, an alternative means of providing "dual slope" conversions is desired. Such an alternative means should be capable of being implemented in a monolithic integrated circuit chip to reduce cost and should be compatible with digital control portions of the system also being formed in such a chip.